FinFETs have emerged as an effective approach to support the scaling of integrated circuits, as FinFETs require less area than planar transistors. FinFETs utilize fin structures of semiconductor material that function as channels for the FinFETs. Fin structures are generally formed on a semiconductor substrate through typical semiconductor patterning processes.
The continued scaling of integrated circuits has generated a demand for methods for forming nanometer-sized features, such as fin structures, that are separated by nanometer-sized distances. As the limits of optical resolution are approached in current lithography processes, double patterning processes have been used to create critical dimensions (CD) and spaces that are beyond the capability of a single lithography step. Specifically, while a conventional lithographic process can be used to form a line-width equal to a minimum critical dimension associated with the lithographic process, a double patterning process can be used to form a line-width smaller than the minimum critical dimension. Double patterning techniques include “pitch split” (also called litho-etch litho-etch, or LELE) and self-aligned double patterning (SADP), also called sidewall image transfer (SIT). To obtain even smaller feature sizes and spacing, self-aligned quadruple patterning (SAQP) or double SIT techniques have been proposed.
Conventionally, fin structures are formed as a “sea of fins” across the entire semiconductor substrate under processing. Then, conventional processing is used to form block masks over selected fin structures and to etch those fin structures not covered by the block masks. During a typical fabrication process, a semiconductor substrate may have block masks of ten or more sizes positioned over fin structures in various selected areas of the substrate. Further conventional processing may include formation of a trench mask that exposes portions of the selected fin structures to define fin structure lengths and fin structure terminal locations on the semiconductor substrate. As integrated circuit features shrink, it becomes difficult to precisely form and position variably-sized block masks over selected fin structures.
Accordingly, it is desirable to provide methods for fabricating integrated circuits that provide for the formation of fin structures only in selected areas of semiconductor substrates. Further, it is desirable to provide methods for fabricating integrated circuits that use masks having trenches bounding non-selected fin structures for removal. In addition, it is desirable to provide methods for fabricating integrated circuits that use masks having trenches of no more than two critical dimensions to expose non-selected fin structures for removal. Furthermore, other desirable features and characteristics will become apparent from the subsequent detailed description and the appended claims, taken in conjunction with the accompanying drawings and the foregoing technical field and background.